Receiver testing has long been an enigma in the serial Data-Com industry due to its complexity and difficulty in sensing bit error conditions. Conventional receiver test systems typically include a high speed signal generator and an integrated bit error detector. This description broadly describes a conventional BERT (Bit Error Rate Tester).
Circuit designers design their circuitry to be tolerant of real world induced jitter influences (typically measured in UI's or Unit intervals of jitter). Their design specifications call out several key types of jitter for which their components need to undergo testing. The typical components of jitter tested are as follows.
Rj (Random Jitter) which may be 0.166 UI of peak-to-peak random jitter measured or extrapolated out to a particular bit error rate which is typically 10E12.
Sj (Sinusoidal Jitter) which also is typically limited to the 0.166UI range of jitter contribution for most standards. Sj is unique in that it is easily generated with a sine wave generator and thus has a characteristic frequency.
ISI (Intersymbol Interference or Data Dependant Jitter) is jitter which results from the signal dispersion effects in an electrical channel which has frequency dependant loss. A cable for instance is a great source of ISI because it has a frequency roll-off. The greater the slope of this roll-off, the more ISI is generated. Fundamentally, ISI is an artifact of the different spectral data content in a normal data transmission system, and the interaction of that spectral content with the transmission media.
ISI historically has been generated by use of an ISI generator board, which comprises a carefully designed set of lossy transmission lines from which a known and predictable amount of ISI can be introduced into the signal stream.
ISI modeling and generation is very important in receiver tolerance test systems, because it is the single most significant real world influence on the signal degradation. Cables, backplanes, and interconnects all introduce substantial amounts of ISI.
Most modern data-com receiver test specifications also call for an amount of ISI equal to that of SJ. Thus, 0.166UI of ISI is also a common test target for ISI.
An ISI generator board 100, as known from the prior art, is shown in FIG. 1. Typically, an ISI generator board has a multitude of differential circuit traces on it 110, 120, 130 and a test engineer must select the trace which introduces approximately the right amount of ISI for testing any given spec or standard. Once the engineer has selected the appropriate trace, he typically leaves the ISI component at this fixed value.
The next step in a receiver test, by convention and history, is to sweep the Sinusoidal Jitter fundamental frequency to map out the points where the receiver's circuitry begins to trigger error conditions. This sweeping is accomplished by slowly increasing the Sj magnitude at a fixed frequency until the Device under test (DUT) fails. Thereafter, the Sj component is reset to 0, the next higher adjacent frequency is selected, and the process is repeated. This is how Bit Error Rate Testers (BERTs) work today.
The above-described operation results in a Jitter tolerance curve 210 as shown in display screen 200 of FIG. 2, which is known from, for example, a J-Bert system manufactured by Agilent Corporation.
As noted above, sweeping SJ has been done historically because it's easy to do. However, it is submitted that the data-com industry does not benefit to a great extent from a sweep of Sinusoidal Jitter (SJ), because no commercial equalizer in existence can compensate for SJ.